1. Field of Invention
This invention relates to a bumping process. More particularly, the present invention is related to a method of increasing the height of bumps without utilizing increasing the thickness of the photo-mask.
2. Related Art
In this information explosion age, integrated circuits products are used almost everywhere in our daily life. As fabricating technique continue to improve, electronic products having powerful functions, personalized performance and a higher degree of complexity are produced. Nowadays, most electronic products are relatively light and have a compact body. Hence, in semiconductor production, various types of high-density semiconductor packages have been developed. Flip chip is one of the most commonly used techniques for forming an integrated circuits package. Moreover, compared with a wire-bonding package or a tape automated bonding (TAB) package, a flip-chip package has a shorter electrical path on average and a better overall electrical performance. In a flip-chip package, the bonding pads on a chip and the contacts on a substrate are connected together through a plurality of bumps formed by the method of bumping process. Accordingly, the technology of bumping process becomes more and more important in the advanced packaging fields.
As mentioned above, the bumping process mainly comprises forming an under bump metallurgy layer on the bonding pads of the wafer and forming bumps on the under bump metallurgy over the bonding pads. After the wafer with bumps formed thereon is singulated into a plurality of individual bumped chips, the bumped chips are attached to the substrates through bumps respectively. However, when the gap between the bumped chip and the substrate is not small, the bumps connecting the substrate and the chip will bear larger shear stress and more easily damaged for that the coefficient of thermal expansion (CTE) of the chip is different from that of the substrate. In such a manner, forming higher bumps to have a larger gap between the chip and the substrate will have the bumps to be able to bear larger shear stress and enhance the mechanical strength of the bumps.
FIG. 1 to FIG. 4 are partially enlarged cross-sectional views showing the progression of steps in a conventional method of forming a bump on a surface of a chip.
As shown in FIG. 1, a wafer 100 is provided. The wafer 100 has a passivation layer 102 and a plurality of bonding pads 104 (only one of the bonding pads is shown) exposed out of the passivation layer 102. Next, an under bump metallurgy layer 106 is formed on the wafer 100 to cover the passivation layer 102 and the bonding pads 104. Generally speaking, the under-ball metallurgy layer 106 mainly includes an adhesion layer 106a, a barrier layer 106b and a wetting layer 106c. Then, the, referring to FIG. 2, solder bumps 110 are formed by providing a patterned photo-resist layer 108 on the under bump metallurgy layer 106 to form a plurality of openings 108a to expose the portions over the bonding pads 104 and filling solder material in the openings 108a to dispose on the under bump metallurgy layer 106 not covered by the photo-resist layer 108. Moreover, the volume of the solder bump 110 is increased through utilizing increasing the thickness of the photo-resist layer 108. Therein, the solder material is filled into the opening 108a of the patterned photo-resist layer 108 through electro-plating to form higher solder bumps 110 by said thicker photo-resist layer. Generally speaking, the opening 108a of the patterned photo-resist layer 108 is ranged between about 100 μm and about 120 μm in size and the thickness of the photo-resist layer 108 is about 100 μm or about 120 μm.
Next, referring to FIG. 3 and FIG. 4, after photo-resist layer 108 is moved, the solder bumps 110 are taken as a mask to etch the under bump metallurgy layer 106 not covered by the solder bumps 110 to form patterned under bump metallurgy layer 106′ until the passivation layer 102 is exposed. Finally, the solder bumps 110 are reflowed to form ball-like solder bumps 112 and enhance the attachment of the ball-like solder bumps 112 to the patterned under bump metallurgy layer 106′.
As we know, the height of the solder bumps after reflowing is pertinent to the volume of the solder material filled into the opening defined by the thickness of the photo-resist layer and the area of the under bump metallurgy for disposing the solder material thereon. Accordingly, when the opening of the patterned photo-resist layer is smaller, there are usually needed more thicker patterned photo-resist layers to be stacked with each other in order to meet the volume of the openings for filling the solder material on condition that the area of the under bump metallurgy layer for disposing the solder material thereon keeps unchanged. However, in photolithography process, it is difficult to form smaller and deeper openings, such as the diameter or width of the opening smaller than 100 μm and the depth of the opening ranged between 100 μm and 140 μm, in the photo-resist layer. Thus, the reliability of forming higher bumps will be lowered.
On the contrary, when the opening of the patterned photo-resist layer becomes larger, the area with solder material disposed thereon to be regarded as the mask for etching the under bump metallurgy will become larger. Accordingly, the area of the patterned under bump metallurgy layer over the bonding pad will become larger and the height of the solder bumps after reflowing will become smaller.
Therefore, providing another method for forming bumps to solve the mentioned-above disadvantages is the most important task in this invention.